With recent progress in semiconductor technology, operating speeds of devices formed in a semiconductor integrated circuit have been significantly increased. One technical problem to be solved to increase the operating speeds is how to distribute at a high speed to such various devices in a semiconductor integrated circuit, a clock signal which defines the operating speeds of the devices.
One proposal is to synchronize the phase of a clock signal to be applied to the various devices in the semiconductor integrated circuit with the phase of an externally applied clock signal by means of a phase-locked loop circuit formed in the semiconductor integrated circuit, to thereby avoid delay which could be imparted when the clock is applied to the respective devices.
On example of an analog-type phase-locked loop circuit used for such a purpose is shown in FIG. 1. This circuit is substantially the same as the one disclosed in IEEE JOURNAL 0F SOLID-STATE CIRCUITS, Vol. 22, No., Apr. 2, 1987, pages 255-261.
In this circuit, a clock signal generated by a voltage controlled oscillator 10 is decoded into four-phase oscillation output signals .phi.1, .phi.2, .phi.3 and .phi.4, by means of a decoder and buffer 12.
The signal .phi.1 is applied to a phase comparator 14 for phase comparison with a reference clock signal REF, and the comparator 14 provides an UP signal or a DOWN signal to a charge-pump circuit 16 in accordance with the phase difference.
The charge-pump circuit 16, upon receiving the UP or DOWN signal from the comparator 14, provides positive or negative charge as a pulse signal to a loop filter circuit 18.
The function of the loop filter circuit 18 is to smooth the pulse signal from the charge-pump circuit 16. The loop filter circuit 18 includes resistors 20 and 22 connected in series with the junction between them providing an output node of the circuit 18. The output signal from the charge-pump circuit 16 is applied to the end of the resistor 20 remote from the junction. A capacitor 24 is connected between the end of the resistor 22 remote from the junction and a point of ground potential. The smoothed output signal from the loop filter circuit 18 is applied to the voltage controlled oscillator 10 as a control signal therefor.
Assume, for example, that the phase of the oscillator output signal .phi.1 lags relative to the phase of the reference clock signal REF. The phase comparator 14 provides, as the UP signal, a pulse signal having a width corresponding to the phase difference between the oscillator output signal .phi.1 and the reference clock signal REF, and places the DOWN signal to a low level. This causes the charge-pump circuit 16 to supply positive charge in an amount corresponding to the phase difference to the loop filter circuit 18. The loop filter circuit 18 integrates the thus supplied positive charge so as to gradually increase its output voltage. As a result, the oscillation frequency of the voltage controlled oscillator 10 slightly rises to reduce the phase difference of the oscillator output signal .phi.1 from the reference clock signal REF. This operation is repeated until the oscillator output signal .phi.1 coincides in phase with the reference clock signal REF.
In case that the oscillator output signal .phi.1 leads in phase the reference clock signal REF, the phase comparator 14 provides a pulse signal having a width corresponding to the phase difference as the DOWN signal, and places the UP signal to the low level. Then, the charge-pump circuit 16 supplies negative charge corresponding to the phase difference represented by the DOWN signal to the loop filter circuit 18, which integrates the thus supplied negative charge and lowers its output voltage. This causes the oscillation frequency of the voltage controlled oscillator 10 to slightly decrease, which, in turn, reduces the phase difference of the oscillator output signal .phi.1 from the reference clock signal REF. Such operation is repeated until the oscillator output signal .phi.1 coincides in phase with the reference clock signal REF.
According to the disclosure in this publication, in order for the phase-locked loop circuit to operate to make the phases of the reference clock signal REF and the oscillator output signal .phi.1 coincide with each other, the phase-locked loop circuit must operate in a such a state that .omega..sub.i .tau..sub.2 and K.tau..sub.2 are located in a stable region which is on the right side of stability limit lines 26 and 28 shown in FIG. 2. In FIG. 2, .omega..sub.i on the abscissa represents an angular frequency (=2f.pi., where f is the frequency of the reference clock signal REF) of the reference clock signal REF, .tau..sub.2 represents the time constant provided by the resistor 22 and the capacitor 24, K on the ordinate is equal to K.sub.O I.sub.P R2 where K.sub.O is the gain of the voltage controlled oscillator 10 (i.e. a value showing the change of the oscillation frequency of the voltage controlled oscillator 10 for a change in the output voltage of the loop filter circuit 18), I.sub.P is the maximum current flowing through the resistor 20 (which decreases as the resistor 20 has a larger value), and R2 is the value of the resistor 22. The stability limit line 26 is for a theoretical delay time td of 0.1.tau..sub.2, and the line 28 is for a theoretical delay time td which is equal to 0.
As will be understood from FIG. 2, if the frequency of the reference clock signal REF must be changed largely, the gain of the voltage controlled oscillator 10, and the values of the resistors 20 and 22 and the capacitor 24 which constitutes the loop filter circuit 18 must be designed anew so that the .omega..sub.i .tau..sub.2 and K .tau..sub.2 can be located in the stable region on the right side of the stability limit lines 26 and 28.
Conventional phase-locked loop circuits have been designed on the basis of the frequency of the reference clock signal REF determined according to customers' request, and the voltage controlled oscillator 10, the loop filter circuit 18 etc. are designed for the thus determined reference clock signal frequency. Thereafter, mask patterns are prepared based on the thus designed circuit configuration for manufacturing the particular phase-locked loop circuits desired by customers. That is, conventional phase-locked loop circuits are custom-designed devices.
There is a desire to provide semi-custom semiconductor integrated circuits, such as gate arrays, which include a phase-locked loop circuit therein for synchronizing a signal with an externally supplied clock signal and supplying the thus synchronized signal to various devices formed by the gate array. However, the frequency of the externally supplied clock signal varies depending on customers' orders. Therefore, in order to produce a gate array including a phase-locked loop circuit, such gate array must be made only after designing the voltage controlled oscillator 10, the loop filter circuit 18 etc. forming the phase-locked loop circuit for a particular frequency desired by a particular customer. This disadvantageously lessens the advantage of the gate array of being a general-purpose device.